AnyCore is two things:
an ideal called a "universal superscalar core",
and a tool that enables research towards this ideal.
A universal superscalar core is a single core that can mimic arbitrary fixed cores in a large superscalar design space,
defined by superscalar structure sizes, superscalar widths, and pipeline depth.
Each of its hundreds of core configurations achieves the same instructions-per-cycle (IPC), frequency, and energy consumption
as the corresponding fixed core design, had that fixed core been individually fabricated.
In other words, a universal superscalar core is "core-accurate" with respect to hundreds or thousands of fixed cores.
Pursuit of a universal superscalar core requires a hardware model of one.
To this end, we developed a register-transfer-level (RTL) design of a comprehensively adaptive superscalar core,
The RTL description of the core is heavily parameterized,
allowing AnyCore processors of different sizes to be synthesized.
A given AnyCore processor is adaptive,
i.e., its widths and structures can be dynamically adjusted within its maximum dimensions.
The RTL description is paired with a Unified Power Format (UPF)
description of power domains, which today's EDA tools can handle for
automatically synthesizing, simulating and measuring power-gated designs.
We are doing both research and chip fabrication with AnyCore.
R. Basu Roy Chowdhury, A. K. Kannepalli, S. Ku, and E. Rotenberg.
AnyCore: A Synthesizable RTL Model for Exploring and Fabricating Adaptive Superscalar Cores.
Proceedings of the
2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'16),
Presented at 2nd RISC-V Workshop on June 30, 2015, by R. Basu Roy Chowdhury.
Experiences with Two FabScalar-based Chips.
Presented at WARP on June 14, 2015, by E. Forbes (H3 project) and R. Basu Roy Chowdhury (AnyCore project).
This project is supported by NSF grant CCF-1018517 (AnyCore: A Universal Superscalar Core),
and a Qualcomm gift.
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